This invention relates generally to the field of semiconductor device manufacturing, more particularly to combinatorial processing of semiconductors with the determination of electrical properties of such devices, and most particularly to determining contact resistance and Schottky barrier height in a manner compatible with combinatorial processing.
Semiconductor electronic devices are found in virtually every segment of the modern economy. Continual efforts are made to improve such devices, to develop new, better and cheaper devices, to improve the materials used in such devices and to improve manufacturing processes. There is an on-going need in the art for improvements in all aspects related to semiconductor device design, manufacturing and use.
A typical semiconductor device includes numerous different materials, interfaces between materials and subsystems whose electrical, thermal, chemical and mechanical properties affect the overall performance of the device. Different semiconductor materials with different dopants and doping levels are typically present, along with various conductors and insulators, all in various geometric configurations with numerous interfacial regions where such materials come into contact, may blend to form alloys or distinct compounds. Additional complexity can arise from effects of processing. For example heat treatments of a metal-silicon interface can lead to the formation of silicides. Analogous changes may occur when other interfaces are subjected to thermal or other processing steps. Thus, in designing such devices, or striving to improve the materials and/or manufacturing processes, it is important to know the properties of such materials and interfaces and how such properties are expected to change in response to contemplated changes in materials, geometry and/or processing.
Techniques for conducting dozens or even hundreds of experiments in parallel have been developed, and continue to be developed, under the general label “combinatorial processing.” These techniques obviously speed up R&D by a tremendous factor, allowing numerous tests to be conducted, and data collected, concurrently. One recent discussion of combinatorial techniques applied to materials science can be found in “Combinatorial Materials Science” by B. Narasimhan et al (eds)., Wiley-Interscience (2007). In particular, various materials, geometries and processing conditions for the manufacture of semiconductor devices can be tested in parallel, exemplified by the specific applications of combinatorial processing to semiconductor devices by Intermolecular, Inc. of San Jose, Calif., employing their High-Productivity Combinatorial™ (HPC™) technology and various devices and procedures related thereto. Such technologies also are known as high-throughput combinatorial technology or combinatorial technology. For economy of language we refer generally to such combinatorial techniques as HPC.
The semiconductor device industry continually has the challenge of developing techniques for determining properties of candidate materials, interfaces and/or structures for semiconductor devices that can be effectively used in combination with HPC processing. Thus, a need exists in the art for improved techniques of determining properties related to semiconductor device performance that are compatible with HPC processing.